First Order Sigma Delta Modulator Design using Floating Gate Folded Cascode Operational Amplifier

Power consumption is the major issue in VLSI design. In this paper an efficient low power first order sigma delta modulator is designed for oversampled ADC using floating gate folded cascode operational amplifier, in 0.35 μm Technology. Floating gate MOSFET have low power Dissipation hence it is an attractive solution in design of data converters, low voltage op -amp with rail-to-rail input and the four quadrant multiplier circuits in lowvoltage analog signal processing. This paper firstly concerns with determination of nonidealities. The nonidealities investigated are clock jitter, thermal noise, circuit leakage, and limited slew rate and gain bandwidth product of Opamp. These all nonidealities are overcome here by using folded cascode Opamp at integrator stage with DC gain 56db ,slew rate of 3.633v/μs ,and gain bandwidth product 14.6MHz .Finally, a first order sigma delta modulator implemented using power supply of ±2.5V using Tanner EDA. General Terms VLSI Circuit Design, Experimentation, Performance, Simulation.